A sense amplifier for semiconductor memory devices compares the current sunk by a selected memory cell with a reference current, typically provided by a reference cell that is structurally identical to the memory cell. A current/voltage converter (“I/V converter”), typically having a pair of transistors in current-mirror configuration, transforms the two current signals into corresponding voltage signals, which are provided to a comparator. The comparator amplifies the differential voltage signal at its input and provides an output binary signal whose state corresponds to the value stored in the memory cell.
A similar sense amplifier for memory devices is, for example, described in U.S. Pat. No. 6,128,225. In this amplifier the current of the memory cell is provided to the input branch of a current mirror, in such a way as to be mirrored on the output branch connected to the reference cell.
The continuing requests for higher density memories and the industrial need for a reduction in the cost per storage bit have led to the development of techniques in which a single memory cell is adapted to store more than a single bit.
A typical non-volatile memory cell includes a MOS transistor whose threshold voltage is varied for storing the desired information, for example by injecting charges into a floating gate. Accordingly, the current sunk by the memory cells in determined biasing states varies depending on the information stored therein. In particular, for storing more than a single bit in one memory cell more than two different threshold voltage values (or levels) for the cells are provided, with each one associated with a different logic value. Such memory cells are then referred to as multilevel.
However, the constant trend toward having smaller dimension manufacturing processes determines a reduction in the current sunk by the memory cell, so the current differences to be detected become smaller and smaller (on the order of a few microamperes). Moreover, it is desired that the asynchronous access time of the multilevel memories is kept comparable with that of the bi-level memories. Thus, for reading the multilevel memory cells it is necessary to implement sense amplifiers that are more sensitive and complex.
According to a known reading technique of a multilevel memory device (called “parallel reading”), the content of the cells is read by simultaneously comparing the current of the memory cell to be read with more reference current values. Typically for those devices parallel sense amplifiers are used.
Referring to FIG. 1, a parallel sense amplifier 100 for quadri-level memories is schematically shown. This sense amplifier is of the type described in Italian Patent Application No. MI2003A 000075, which is in the name of the assignee of the present invention. Such a sense amplifier 100 includes a measure branch 105m for receiving the cell current Im to be measured and three reference branches 105r1–105r3, each one for receiving a reference current Ir1–Ir3, for example generated by reference cells.
The multilevel memory cell can be programmed in a plurality of states, in this example four, which are associated with corresponding ranges of the cell threshold voltage (depending on the electrical charge accumulated on the floating gate). Each programming state represents a different logic value so that the quadri-level memory cell stores a logic value which consists of two information bits B1B0 (i.e., the logic value 11, 10, 01 or 00, by the usual convention associated with increasing values of the threshold voltage).
When the selected memory cell is biased in an appropriate way, a cell current Im delivered thereby corresponds to the stored logic value. The cell current Im is read by the sense amplifier, which compares such current Im with the reference currents Ir1–Ir3 in order to decode the corresponding logic level.
FIG. 2 represents a diagram showing the relation between the cell currents and the reference currents in the case of a four-level memory. In particular, a horizontal axis I represents possible values of currents of the memory cells and the reference currents.
Im1, Im2, Im3 and Im4 represent possible values of current sunk by memory cells in each one of the four possible programming states. In detail, Im1, Im2, Im3 and Im4 are supposed to be the average values of statistical distributions of memory cell currents in the different programming states, corresponding to the logic values 11, 10, 01 and 00, respectively. In particular, under the same biasing conditions, the memory cell programmed to the logic value 11 presents a low threshold voltage so it provides a high current Im1. The current provided by the memory cells decreases with the increase of the threshold voltage, until it becomes very small (possibly zero) when the memory cell is programmed to the logic value 00.
Ir1, Ir2 and Ir3 are values of reference currents used for discriminating the four possible programming states of the quadri-level memory cells under reading conditions. Each pair of adjacent logic values is discriminated by using the reference current Iri (i=1, 2, 3); for example, the memory cell is considered to be programmed to the level 10 when its current is between the reference current Ir2 and the reference current Ir1. As described in detail below, for reading each selected memory cell a parallel sense amplifier is used, which simultaneously compares the cell current Im with the three reference currents Ir1–Ir3.
Referring back to FIG. 1, each branch 105m and 105r1–105r3 of the sense amplifier 100 includes a PMOS transistor 115m and 115r1–115r3, acting as a load. The PMOS transistor 115m of the measure branch 105m is diode-connected (i.e., the gate terminal thereof is short-circuited with the drain terminal thereof). The PMOS transistors 115m and 115r1–115r3 have their source terminals connected to a voltage supply terminal, which provides the voltage +Vdd, and their gate terminals are connected together. The drain terminals of the PMOS transistors 115m and 115r1–115r3 are referred to as “load nodes” LOADs and LOADr1–LOADr3, respectively.
An equalizing NMOS transistor 125r1–125r3 connects each reference branch 105r1–105r3 to the measure branch 105m. In particular, the equalizing transistor 125r1–125r3 has a first terminal connected to the corresponding load node LOADr1–LOADr3 and a second terminal connected to the load node LOADs. The gate terminals of the equalizing NMOS transistors 125r1–125r3 are controlled by an equalization signal EQ; in particular, the equalization signal EQ is at the logic level 0 when de-asserted and at the logic level 1 when asserted.
A comparator 130r1–130r3, consisting of a differential amplifier, is associated with each reference branch 105r1–105r3. In particular, the inverting input terminal (“−”) of each comparator 130r1–130r3 is connected to the corresponding load node LOADr1–LOADr3, whereas the non-inverting input terminals (“+”) of all the comparators 130r1–130r3 are connected to the load node LOADs.
In the above-described architecture of the parallel sense amplifier 100, each PMOS transistor 115r1–115r3 on the reference branches 105r1–105r3 forms a current mirror with the PMOS transistor 115m on the measure branch 105m; such current mirrors are connected in parallel to each other. Each current mirror mirrors the unknown cell current Im on the three reference currents Ir1–Ir3. The difference between the cell current Im and each one of the reference currents Ir1–Ir3 then generates a difference between the voltages at the input terminals of the corresponding comparators 130r1–130r3.
Accordingly, each comparator 130r1–130r3 amplifies the voltage difference between the load node LOADs and one of the load nodes LOADr1–LOADr3. The output terminal of each comparator 130r1–130r3 generates a comparison signal out1–out3 indicative of the result of the comparison between the currents.
When the equalization signal EQ is asserted, the equalizing transistors 125r1–125r3 are turned on and permit the pre-charge current to flow within the matrix and reference branches 105m and 105r1–105r3 and equalize the voltage at the terminals LOADs and LOADr1–LOADr3. This phase is referred to as “pre-charge/equalization phase” and has a duration such that it permits the biasing stabilization of the sense amplifier 100 and the cell current Im. Such a pre-charge/equalization phase also insures the comparator 130r1–130r3 does not wrongly amplify the pre-charge signal.
The structure just described, although satisfactory under many aspects, is however affected by a problem which will now be illustrated.
Let for example the case be considered in which the cell current Im is greater than the reference currents Ir1–Ir3 (a typical case of cells storing 11). In the pre-charge/equalization phase, the measure branch 105m is also pre-charged thanks to the current contribution coming from the load nodes LOADr1–LOADr3 of at least some of the reference branches 105r1–105r3, in particular of the branch 105r3 and, in lower amount, of the branch 105r2. The reference branch 105r1 in turn receives current contributions from the reference branch 105r3 and, in lower amount, from the reference branch 105r2. The load nodes LOADs and LOADr1–LOADr3 are then caused to assume a biasing voltage with a value different from their operating steady-state value when the equalizing transistors 125r1–125r3 are turned off. In particular, the load node LOADs is caused to assume a biasing voltage with a value higher than expected.
As a consequence, in an “evaluation phase”, when the equalization signal EQ is de-asserted (i.e., the equalizing transistors 125r1–125r3 are turned off), the load nodes LOADr1–LOADr3 require a given time interval for reaching their steady-state value. Such a time interval cannot be evaluated a priori, since it depends also on the stray capacitive load at the load nodes LOADs and LOADr1–LOADr3 and on the unknown differential current signal.
FIG. 3 shows a diagram of the voltages at the load nodes LOADs and LOADr1–LOADr3 versus time in the parallel sense amplifier of FIG. 1 in the above-described case, wherein the cell current Im is greater than the reference current Ir1.
During the pre-charge/equalization phase (i.e., signal EQ at logic level 1), as described above, the load node LOADs, and then the gate terminal of the PMOS transistors 115m and 115r1–115r3, are brought towards a voltage greater than the steady-state one.
In the successive evaluation phase (i.e., signal EQ at logic level 0), the diode-connected PMOS transistor 115m is initially run through by a current lower than the steady-state one, equal to the cell current Im, since, at the end of the pre-charge/equalization phase, at the load node LOADs there are current contributions provided by the reference branches. For the balance of the currents at the node LOADs, when the equalizing transistors 125r1–125r3 are turned off, the voltage of the load node LOADs, coinciding with the voltage of the gate of the PMOS transistors 115m and 115r1, tends immediately to decrease.
Also the PMOS transistor 115r1 is initially run through by a current lower than the steady-state one, which is equal to the reference current Ir1, and, moreover, the voltage at its gate terminal is determined by the decreasing of the voltage at the node LOADs. In response to the greater current request, the voltage at the load node LOADr1 will tend first to decrease, until the gate voltage of the PMOS transistor 115r1 is not sufficiently decreased, then to increase again, in a second time, up to the correct steady-state value.
On the contrary, the voltage of the load node LOADr3 tends to rapidly increase towards its steady-state value. Also the load node LOADr2 tends immediately to increase towards its steady-state value, although with a less rapid transient.
The above-described transient generates a “belly effect” on the curve representing the voltage at the load node LOADr1, when the currents to be discriminated are close to each other, bringing an inversion of the voltages at the load nodes, which can lead to errors in the reading operation, unless the evaluation phase is properly extended. The “belly effect” is also related to the difference between the capacitive load on the two matrix branches 105m and 105r1.